Traditionally, contacts for connecting current electrodes to a transistor have been formed on respective surfaces of source and drain regions. Contacts formed on surfaces of source and drain regions, however, pose problems with current flow in three-dimensional devices, such as FinFET transistors or tri-gate transistors. In particular, as shown in FIG. 1, a conventional FinFET transistor 10 is shown. Conventional FinFET transistor 10 may be formed on a substrate layer, such as oxide layer 12. Conventional FinFET transistor 10 may include a source/drain structure 14, a fin 16, a fin cap 18 formed on fin 16, and a gate 22 formed on a gate dielectric 20. A source/drain contact 24 may be formed on source/drain structure 14 after a silicide layer 27 is formed on source/drain structure 14. As shown in FIG. 1, current flows along the fin's (e.g., fin 16) sidewalls as shown by directional arrows 26. The current then flows to the source/drain contact 24, as indicated by directional arrows 28. Because the source/drain contact is formed only on the surface of source/drain structure 14, current flowing along the bottom part of the fin incurs higher resistance, since it has to travel a longer path before getting to source/drain contact 24. This results in a higher effective source/drain resistance for such conventional FinFET transistors. Although FIG. 1 shows current flowing from the bottom part of fin 16 to source/drain contact 24, current also flows from a source/drain contact on the other side of fin 16 to the bottom part of fin 16. This results in additional resistance to current flows in a conventional FinFET transistor.
In addition, traditionally, gates on conventional MOSFET devices are contacted at the top of the gate electrode material, outside the active region. However, as gate thickness is being reduced, the gate resistance is becoming a problem. In particular, in many instances the gate electrode is a laminate of several materials. Typically, the bottom layer is a low-resistance conductor and rest of the gate is made of doped polysilicon or metal silicides. In any case, the materials forming the rest of the gate have higher resistivity. The gate contact is thus separated from the bottom layer having a low resistivity and is instead in contact with the rest of the layer having a high resistivity.
Thus, there is a need for a transistor with a lower source/drain resistance and lower gate resistance.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.